1. Field of the Invention
The present invention relates to a fabrication process used to create a dynamic random access memory, (DRAM), device, on a semiconductor substrate, and more specifically to a process used to create a storage node structure, with increased surface area.
2. Description of the Prior Art
As the density of DRAM cells increase to levels greater than 1 billion bytes per cell, the area allotted for the DRAM capacitor structure has been decreased. Smaller capacitor structures, presenting decreased capacitor surface area, can result in a decrease in DRAM capacitance, and thus in decreased DRAM performance. Several solutions to the decreasing size of the DRAM capacitor structure, in regards to maintaining, or increasing capacitor surface area, and thus maintaining, or increasing DRAM performance, have been offered. For example the use of a hemispherical grain, (HSG), silicon layer, as a surface layer for a DRAM capacitor, storage node structure, has been used to increase capacitor surface area. The concave and convex features of an HSG silicon layer, used as the surface layer of a storage node structure, offers increased surface area, and thus increased capacitance and DRAM performance, when compared to counterpart storage node structures, fabricated with smooth surfaces. Prior art, such as Tsai, in U.S. Pat. No. 5,763,306, as well as Watanabe et al, in U.S. Pat. No. 5,723,379, describe processes for forming HSG silicon layers, for DRAM capacitor storage node structures, however the procedures needed for successful formation of HSG silicon, are difficult to control. For example the temperature used for HSG silicon formation, comprised of a deposition, and an anneal procedure, have to be controlled to within about 3.degree. C., throughout the used deposition or furnace apparatus, to result in the attainment of a successful HSG silicon layer.
This invention will describe a procedure used to create a DRAM capacitor, storage node structure, with a roughened surface, needed for the increased surface area, and capacitance, however via use of a roughened surface, tungsten silicide layer, rather than the difficult to control HSG silicon layer. The tungsten silicide layer is roughened via subjection to an oxidation procedure, followed by the removal of the previously created oxide layer. This sequence provides a tungsten silicide layer, used as the top layer of a storage node structure, with a roughened top surface, comprised of concave and convex features, thus offering the surface area increases, needed for capacitance and performance improvements.